1. Field of the Invention
The present invention relates generally to semiconductor memory devices having changeable word organizations, and more particularly, to an improvement thereon wherein word organization changeover is carried out by on-chip logic circuitry.
2. Description of the Prior Art
FIG. 1 is a block diagram showing schematic structure of an example of a static random access memory (referred to as SRAM hereinafter).
A memory cell array 101 comprises a plurality of word lines, a plurality of bit line pairs arranged intersecting with the plurality of word lines, and a plurality of memory cells each arranged at each of intersections thereof. A row decoder 103 is responsive to address signals applied through a row address buffer 102 for selecting one of the plurality of word lines. A column decoder 105 is responsive to column address signals applied through a column address buffer 104 for selecting one of the plurality of bit line pairs. Data is read out or written from or to a memory cell at an intersection of the selected word line and the selected bit line pair. At the time of reading out data, the data stored in the memory cell selected in the above described manner is outputted through a data output buffer 107 by a read circuit 106. At the time of writing data, data externally applied to a data input buffer 109 is inputted to the memory cell selected in the above described manner by a write circuit 108.
FIGS. 2A and 2B are diagrams showing examples of pin arrangements in which static RAMs having a 1M word by 1 bit organization and a 256 K word by 4 bit organization are mounted, respectively.
In a static RAM shown in FIG. 2A, pins 1 to 6, pins 8 to 11, pins 17 to 20 and pins 22 to 27 are address input terminals receiving address signals A, and a pin 12 is a data output terminal for data Q. The pin 13 is a read/write control terminal receiving a read/write control signal W. The read/write control signal W indicates write operation when the level thereof is an "L" level, and read operation when the level is an "H" level. A pin 14 is a ground terminal receiving a power-supply potential V.sub.SS (generally 0 V). A pin 15 is a chip selecting terminal receiving a chip selecting signal CS. The chip selecting signal CS indicates a selected state when the level thereof is an "L" level and a non-selected state or a standby state when the level is an "H" level. A pin 16 is a data input terminal for data D. A pin 28 is a supply terminal receiving a power-supply potential V.sub.CC (generally 5 V). Pins 7 and 21 are terminals to which no connection is made.
In the static RAM shown in FIG. 2B, a pin 12 is an address signal input terminal, a pin 13 is a chip selecting terminal, a pin 15 is a write/read control terminal, and pins 16 to 19 are data input/output terminals. The other pins are the same as those in the static RAM shown in FIG. 2A.
If the conventional static RAM has different word organizations such as a 1M word by 1 bit organization and a 256K word by 4 bit organization, different devices having different pin arrangements, as shown in FIGS. 2A and 2B, are required.
In the RAM with 1M word by 1 bit organization, one of four data amplified by four sense amplifiers SA is read out through an output buffer, as shown in FIG. 3A.
On the other hand, in the RAM with 256K word by 4 bit organization, four data amplified by four sense amplifiers SA are read out simultaneously through four output buffer, as shown in FIG. 3B.
When the above described RAM is tested, 256K addresses must be selected to select all addresses in the 256K word by 4 bit organization, and 1M addresses must be selected in the 1M word by 1 bit organization. The test time period of the RAM with the 1M word by 1 bit organization is four times that of the RAM with the 256K word by 4 bit organization, in a test pattern referred to as an N pattern such as a march and a checkerboard, and is sixteen times that of the RAM with the 256K word by 4 bit organization, in a test pattern referred tc as an N.sup.2 pattern such as a galloping.
A test by the galloping pattern is performed in the following manner in the RAM having N capacity:
.circle.1 In FIG. 4, data "0" is written in all addresses. Therefore, N operations are required.
.circle.2 Data "1" is written in the address 0. Thus, one operation is required. Data are read out sequentially from the addresses 1.fwdarw.0.fwdarw.1, 2.fwdarw.0.fwdarw.2, . . ., N-1.fwdarw.0.fwdarw.N-1. In this case, 3(N-1) operations are required. Data "0" is written in the address 0. In this case, one operation is required.
.circle.3 The same operations as the above .circle.2 are repeated increasing the address one by one.
Operations .circle.1 and .circle.3 are performed by inverting data "0" into data "1" and data "1" into data "0".
As a result, the following operations are required: EQU 2.times.{N+N[3(N-1)+2]}=6N.sup.2
Thus, assuming that a cycle time is 25 ns, a test time period (6N.sup.2)T is as follows in the case of the RAM with 1M word by 1 bit organization: ##EQU1##
On the other hand, in the case of the RAM with 256K word by 4 bit organization, a test time period is one sixteenth of that of the RAM with 1M word by 1 bit, that is, about three hours.
Thus, even if the RAM with the 1M word by 1 bit organization and the RAM with the 256K word by 4 bit organization have the same memory capacity such as 1M bits, the test time period depends on the word structure.
A 256K.times.1/64K.times.4 word organization is changed by exchanging photomasks in an aluminum process, which is described in an article entitled "25-ns 256K.times.1/64K.times.4 CMOS SRAM's", IEEE Journal of Solid State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 686-691. In addition, the test time period is reduced by grouping memory cells, which is disclosed in Japanese Patent Laying-Open Gazette No. 39300/1986.
Since the conventional semiconductor memory device had the above described structure, the test time period was significantly changed depending on the word organization even in devices having the same memory capacity. Particularly, a semiconductor memory device with a 1-bit organization such as a 1M word by 1 bit organization requires the longest test time period.
Additionally, semiconductor memory devices having different word organizations are formed as different devices. Thus, in order to change the word organization of the semiconductor memory device, the semiconductor memory device must be replaced with a different device having a different word organization. Further, different chips must be obtained and kept in inventory. Also the chips require dual characteristics to be not perfectly matched.